A key component of electronic imaging systems such as digital cameras and video cameras is the image sensor electronics. The image sensor electronics includes a sensor array and associated analog and digital processing circuitry. The sensor array captures the light image in electronic form using thousands of photocells. Each photocell provides an electrical signal proportional to the incident light at a portion of the image. These electrical signals are then processed into digital image data by the processing circuitry.
Recent developments in image sensor technology have attempted to reduce the cost of manufacturing the image sensor electronics by integrating the processing circuitry and the sensor array into the same integrated circuit (IC) die. Certain technologies that enable such integration include advanced logic IC fabrication processes such as polycide-gate metal oxide semiconductor (MOS) and salicide-gate MOS. These processes have traditionally been used to manufacture ICs such as microprocessors that have only logic functionality. Attempts have been made to adapt such processes to implement analog functionality and photodetection to develop a high performance, low cost image sensor IC die. See e.g. U.S. Patent Application of Mark Beiley et al., Ser. No. 08/873,987, filed Jun. 12, 1997, entitled A Well-To-Substrate Photodiode For Use In A CMOS Sensor On A Salicide Process now U.S. Pat. No. 6,040,592 ("Beiley"), currently pending; U.S. Pat. No. 5,841,126, issued Nov. 24, 1998 to Fossum, entitled CMOS Active Pixel Sensor Type Imaging System On A Chip. As discussed in Beiley, some of the problems with adapting the conventional logic process for photodetection have been difficulties in designing photocells that respond to incident light efficiently, i.e. have good quantum efficiency, have low leakage noise, and, of course, are relatively inexpensive to manufacture. Because the photocells are part of sensor ICs that are expected to be produced in very large quantities, it is important that the sensor IC be capable of manufacture without significant modifications to the flow of the logic process.
The logic process is conventionally optimized to implement a large number of tiny, densely packed transistors interconnected by multiple layers of metal to support complex logic functions. In conventional polycide-gate or salicide-gate MOS processes, a silicide formation step is performed after the semiconductor regions (usually silicon) corresponding to source, drain, and gate of the transistors in the IC have been formed. Silicide formation calls for depositing a blanket layer of refractory metal, normally everywhere on the surface of the wafer containing the sensor IC die, and then causing a reaction between the deposited refractory metal and any underlying silicon that constitutes the source, drain, and gate regions. One characteristic of such a logic process which is important for photocell design is that the resulting silicide is opaque, and thus prevents incident light from entering the photosensitive regions of the silicon below the surface. The silicided process can be customized for photocell construction by providing an additional mask step that prevents the formation of the silicide over those silicon regions that are used for photocells. However, such an additional mask step substantially increases the cost of manufacturing the IC.